1. Field of the Invention
The invention generally relates to differential switch circuits of the type utilized in digital-to-analog converters (DACs). In particular, the invention relates to the circuitry of a switched current CMOS DAC which latches, drives, and switches the current to one or the other of differential outputs.
2. Description of the Prior Art
DACs generally have comprised a number of switches which are selectively operated by a multi-bit digital input signal to produce corresponding binarily-weighted bit currents to be summed as an analog output signal. Such converters ordinarily are formed as integrated circuits, with each switch comprising two transistors arranged as a differential switch-pair. The individual transistors of such a switch-pair typically are controlled by complementary signal sources which operate to turn one switch on while turning the other switch off. One of the two switches is coupled to a summing bus, and the other switch is coupled to a common line such as ground.
One problem with such prior art switching arrangements is that there is asymmetry in the switch turn-on and turn-off speeds. The switches are generally switched simultaneously to provide valid current levels at the output terminal. However, there is often a delay introduced between the "make" and "break" actions of the switches causing spurious signals, or "glitches", to appear at the output terminal.
Examples of prior art DAC switching techniques are found in U.S. Pat. Nos. 5,703,519, 5,689,257, 5,612,697, 5,450,084, 5,148,164, and 4,721,866. The techniques build on the concept that there should be only one polarity of device used in the clocked pass gates, and dynamic storage of the previous state right at the differential switch is the best way to insure exact timing from the clock. It is important to move the point at which the final differential switch signal is created as close to the current switch as possible.
Unfortunately, the prior art does not include a method of creating the true and complement logic signals which the invention does. The method by which these two logic signals are created and propagated is integral to the invention.
The prior art does not teach the need for exact timing delays from the clock signal to the drivers when used in signal reconstruction from sampled data applications. The prior art does not describe the use of temporary dynamic storage as a means to realign the arrival of the true and complementary signal. The invention involves a method and apparatus to create the optimal true and complement driving waveforms which exploits the property of dynamic storage at the gates of the differential switch.
Some of the critical issues involved in DAC switching are as follows. In standard CMOS logic circuits, the propagation speed of a low to high transition is different to that of a high to low transition and can be altered by the ratio of PMOS to NMOS device strengths. Unequal delay for low to high and high to low transitions from the edge of the clock signal which causes new data to be passed into the output switch of a digital-analog converter causes even order distortion components in the reconstructed output waveform.
In addition, static data storage (latch) generally requires full power rail signal swings where dynamic storage (on a capacitor) can operate with almost any signal levels. It is desirable to limit the magnitude of the signal at the control gates of a differential current switch to be no more than the Vgs of an on switch transistor.